1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an apparatus for recognizing chip identification.
2. Description of Related Art
In the manufacture of semiconductor devices, semiconductor chips are formed on a wafer and a test is usually performed with the semiconductor chips on the wafer to verify that operations of semiconductor chips work properly. If the semiconductor device properly operates, it is packaged through an assembly process and then, a test is performed on the packaged device to determine if the packaged device works properly. If it does, the device can be put on the market for sale. Device and test identification information (so called xe2x80x9cchip IDxe2x80x9d) such as process lot number, wafer number and chip position on the wafer are put on the semiconductor device. When a defective device is later found, whether from device failure or caused by improper handling by users, the chip ID information can be used to aid in determining the cause of the defect. But the xe2x80x9cchip IDxe2x80x9d cannot be read from a packaged semiconductor device. Accordingly, it is often difficult if not impossible to determine whether defects are caused by a random event or caused by certain processes after packaging of a semiconductor device. Without knowing the cause of the defect, it is difficult to reduce the rate of defect.
FIG. 1 shows a chip ID recognition apparatus as disclosed in U.S. Pat. No. 5,294,812. Referring to FIG. 1, a conventional chip ID recognition apparatus comprises a resistor R11, NMOS transistors MN10 through MN1n and fuses F10 through F1n. Each gate of the NMOS transistors MN10 through MN1n is connected to a control signal CON. The fuses are cut by a laser beam according to specifications before an assembly process, and after passing a wafer test. Thus, a power voltage VDD is not transmitted to cut fuses, but to uncut fuses through I/O terminals I/O0 through I/On. If all the fuses F10 through F1n are not cut, the power voltage VDD is connected through transistors MN10 to MN1n to I/O0 to I/On. In contrast, if all the fuses F10 through F1n are cut, the power voltage VDD is cut-off from I/O0 to I/On. The amount of information of chip ID presentable by such circuit depends on the number of cut fuses. For example, when the number of fuses is n, 2n pieces of information can be presented.
FIG. 2 is a diagram illustrating the arrangement of pads of a conventional semiconductor device incorporating the chip ID recognition apparatus shown in FIG. 1. Reference numerals 21 through 2n denote pads connected to the I/O terminals I/O0 through I/On. The conventional semiconductor device requires a plurality of pads for reading information on whether each fuse is cut or not. A circuit for ID recognition placed within a chip requires a greater number of pads for a number of external connection, while it occupies a smaller space due to a fine line width of a circuit in a semiconductor device. The increase in the number of pads may cause the increase of the chip size. Further, the information on chip ID comprises a wafer number and the characteristics of a chip as well as a chip position on a wafer. Therefore, the number of pads increases according to the increase of the number of pieces of information.
Also, the pads 21 through 2n are connected to an external electrode via a package pin. If there is a potential difference between any of the pads 21 through 2n and the external electrode, power is unnecessarily consumed due to leakage current.
Another conventional device is described in Japanese Patent Publication No. 7-192979. The device comprises a bonding determination unit, an ID code-setting unit and an ID code resistor for assigning an ID code for product classification. The device has a large size due to an increase in the number of resistors for storing ID codes.
To solve the above problems, it is an object of the present invention to provide an apparatus for recognizing chip identification (ID) capable of minimizing the number of test pads for ID recognition and recording many pieces of information on the chip ID by employing a simple circuit structure.
It is another object of the present invention to provide a semiconductor device comprising a circuit for recognizing chip identification (ID) capable of minimizing the number of test pads for ID recognition and recording many pieces of information on the chip ID by employing a simple circuit structure.
According to one aspect of the present invention, there is provided an apparatus for recognizing chip identification comprising a counter circuit for counting a clock signal in response to a reset signal and decoding the counted clock signal to produce at least one decoding signal; and a fuse circuit comprising a plurality of fuse arrays, each fuse of the plurality of fuse arrays representing chip identification information, for outputting an output signal indicating whether each fuse of the plurality of fuse arrays is cut in response to the at least one decoding signal.
In a preferred embodiment of the present invention, the counter circuit a counting device comprising N flip-flops (N greater than 1) for counting the clock signal in response to the reset signal and outputting N-bit signals, wherein each flip-flop is connected to each other in series; and a first decoder for combining the bits of the N-bit signals and decoding the combined bits to output the decoded bits as first decoding signals of M-bit; and a second decoder for combining the other bits of the N bit signals and decoding the combined bits to output the decoded bits as second decoding signals of K-bit.
In a preferred embodiment of the present invention, the plurality of fuse arrays comprises K fuse arrays, and each fuse array comprises M fuses. The fuse circuit further comprises a first group of transistors for responding to the first decoding signals, wherein each transistor comprises one end connected a first end of the each fuse; a second group of transistors for responding to the second decoding signals, wherein each transistor is connected between a power voltage and a second end of the each fuse; a pull down transistor connected to the other end of each transistor of the first group of transistors, and for controlling the output signal depending on the power voltage.
According to another aspect of the present invention, there is provided a semiconductor device comprising a plurality of pads for inputting/outputting predetermined signals to an inner circuit during normal operation; a first pad for receiving a reset signal during a test mode for recognizing chip identification; a second pad for receiving a clock signal during the test mode; a circuit for recognizing the chip identification comprising a plurality of fuses for representing chip identification information, for producing an output signal indicating whether each fuse of the plurality of fuses is cut in response to the reset and clock signals; and a third pad for transmitting the output signal of the circuit for recognizing the chip identification information to an external during the test mode.
According to further aspect of the present invention, there is provided a semiconductor device comprising first common pads for inputting predetermined signals during normal operation mode and inputting a reset signal and a clock signal during a test mode for recognizing chip identification; a test pad for inputting an external mode set signal, the mode set signal being enabled during the test mode; a circuit for recognizing the chip identification comprising a plurality of fuses for representing chip identification information, for producing an output signal indicating whether each fuse of the plurality of fuses is cut in response to the reset signal and the clock signal; and a second common pad for transmitting an output signal of an inner circuit to an external during the normal operation mode and transmitting the output signal of the circuit for recognizing the chip identification to the external during the test mode.